1. Technical Field
Methods of manufacturing thin film transistors for semiconductor devices are disclosed wherein an offset area is influenced by a gate voltage to increase the ON-current, which provides a thin film transistor which improves the ON/OFF characteristic of the resulting semiconductor device and, whereby the thickness of a gate insulation layer is reduced, the margin of the device is secured, and the electrical characteristic is superior.
2. Description of the Related Art
The Thin Film Transistor TFT is generally used for manufacturing semiconductor devices such as Static Random Access Memory SRAM devices and Liquid Crystal Displays LCDs. As the integrity of semiconductor devices increases, the operational characteristics of the device depend on the operational characteristics of the thin film transistor.
The SRAM developed recently uses a p-channel poly-silicon thin film transistor as a bottom gate that is a pull-up device, and the thickness of the gate of the thin film transistor has to be reduced according to the recent trend of increased integrity in semiconductor devices which in turn requires a reduction in the operation voltage thereof.
FIG. 1 is a sectional view for illustrating a conventional method for manufacturing a thin film transistor of a semiconductor device. As shown in FIG. 1, a gate electrode 2, a gate insulation layer 3 and a channel area 4 are formed consecutively on the semiconductor substrate 1, to manufacture a thin film transistor.
The gate electrode 2 is formed by patterning a layer that is manufactured by depositing an n-type doped amorphous silicon, or by depositing an undoped poly-silicon and then doping with n-type impurities.
The gate insulation layer 3 is formed by depositing oxide on the gate electrode 2, by a chemical vapor deposition based on a silane (DCS: SiH2Cl2), and the channel area 4 is formed by depositing poly-silicon on the gate insulation layer 3.
However, according to the conventional art, the gate insulation layer 3 formed by the oxide based on the silane (DCS: SiH2Cl2) has a high swing value, and therefore, there are problems in that the ON-current is small and the ON/OFF ratio can be satisfied only marginally.
Accordingly, as the thickness of the gate insulation layer 3 is reduced, the electrical property required for the operation of the device cannot be secured.
To overcome the above-described problems, a method for manufacturing a thin film transistor with a reduced gate insulation layer thickness is disclosed. Using the disclosed method, the margin of the device is secured, and the electrical characteristic becomes superior, as a low swing value and a high ON/OFF ratio are implemented by forming a gate insulation layer of ONO structure on the gate electrode on the semiconductor device and then performing a steam anneal process using a wet-oxidizing method to reinforce the surface of the respective ONO layer.
A disclosed method for manufacturing a thin film transistor of a semiconductor device comprises: forming a gate electrode, after forming an insulation layer on a semiconductor substrate having a certain lower construction; performing a first pre-treatment cleaning process to a resulting structure, and then forming a gate insulation layer of ONO structure; performing a steam anneal process on the result formed with the gate insulation layer; removing the gate insulation layer around a node area of the semiconductor device by performing a masking and an etching processes; performing a second pre-treatment cleaning process on the result, and then forming a channel area on a remaining area excluding the node area; performing an SPG anneal process on the channel area, and performing a light oxidation for a surface treatment of the channel area by In-Situ; and performing a threshold voltage ion injection on the entire channel area, and then performing LDO ion injection and source/drain ion injection consecutively using respective masks on the channel area to form a pull-up transistor.
Another disclosed method for manufacturing a thin film transistor of a semiconductor device comprises: forming a gate electrode after forming an insulation layer on a semiconductor substrate having a certain lower construction; performing a first pre-treatment cleaning process to a resulting structure, and then forming a lower oxidation layer; forming a nitride layer on the lower oxidation layer; forming an upper oxidation layer on the nitride layer to form a gate insulation layer comprised of the lower oxidation layer, the nitride layer and the upper oxidation layer; performing a steam thermal process using a wet-oxidation method on the result formed with the gate insulation layer; removing the gate insulation layer around a node area of the semiconductor device by performing a masking and an etching processes; performing a second pre-treatment cleaning process on the result, and then forming a channel area on a remaining area excluding the node area; performing an SPG anneal process on the channel area, and performing a light oxidation for a surface treatment of the channel area by In-Situ; and performing a threshold voltage ion injection on the entire channel area, and then performing LDO ion injection and source/drain ion injection consecutively using respective masks on the channel area to form a pull-up transistor.
According to the disclosed methods, as a low swing value and a high ON/OFF ratio are implemented by forming a gate insulation layer of ONO structure on the gate electrode on the semiconductor device and then performing a steam anneal process using a wet-oxidizing method to reinforce the surface of the respective ONO layer, the thickness of the gate insulation layer is reduced.